LOCKE Detailed Specification Tables

This document shows the detailed specification of LOCKE coherence protocol for each cache controller, using a table‐based technique [1]. This representation provides clear, concise visual information yet includes sufficient detail (e.g., transient states) arguably lacking in the traditional, graphical form of state diagrams. Table I shows detailed specifications of a L1 cache controller. States, events and actions are represented on it. Each of the rows of the table corresponds to a different possible state a cache line can be in. Each of the columns represents an event triggered by the coherence controller when receiving a message. The entries of the table show the actions that have to be taken on each case and sometimes the state the cache line has to change to (which is represented by '/' followed by the next state). For example: when a cache controller receives a GETX message from another and has the block requested in S state, it must send all the tokens to the requestor and jump to the PS state. If there is no state indicated, the cache line will stay in the same state after executing the corresponding actions. Considering that the meaning of the stable and transient states mentioned is already known by the reader, we will explain the control states specific of LOCKE. The first three of them are states where the controller has sent some kind of data and is waiting for an acknowledgement message. The difference between them is the type of data sent. The PS state indicates that shared data was sent. PX state shows that data and all the tokens were sent (including the owner). PO state indicates that shared data was sent, but the controller still keeps the owner token. This differentiation is made to distinguish when the requests from others are needed to be answered. The last control state is the frozen state (F). A line gets to F when there is a pending write request to the address, but the controller has seen another write request (GETX) with more priority than it. Almost all the times the events are triggered by the coherence controller depending on the messages received. There are some exceptions where the triggered event depends also on the state of the cache line. For example, when the processor issues a load or store operation, the cache controller triggers the load or store event if it has space for the …